In recent years, nonvolatile semiconductor memory devices using MOS transistors with floating gates as memory elements, such as flash memory, have been widely used in information equipment, home electronics, cars, and the like. NAND flash memory in particular has been taking a lead in achieving larger-capacity memory and miniaturizing memory in place of DRAM. With the miniaturization having reached an advanced stage, however, the following difficulties in memory operations have come to the surface: the difficulty of miniaturizing floating gates and others further, the effect of interference between adjacent cells, and a problem with the reliability of tunnel oxide films. Therefore, near-future physical limits on the technology are seen coming.
To realize memory that surpasses flash memory in miniaturization and storage capacity, memory elements that use new materials and operating principles or memory that uses the technique for a three-dimensional layer stack of cell arrays and the like have been considered. One of these new memories is variable-resistance memory.
As variable-resistance memory, magnetoresistive random access memory (MRAM), phase-change RAM (PRAM), and the like have been proposed. MRAM is a memory that uses the tunnel magnetoresistive effect of a magnetic tunnel junction. PRAM is a memory that uses the following property of a chalocogenide semiconductor: Joule heat produced by current causes a chalcogenide semiconductor to undergo phase transition between a crystal phase and an amorphous phase and the chalcogenide semiconductor has a different resistance in each of the phases.
In recent years, variable-resistance memories using variable-resistance materials and operating principles other than MRAMs and PRAMs have been developed actively. The variable-resistance memory is known as resistive RAM (ReRAM).
One of variable-resistance materials used for ReRAM is metal oxide. Variable-resistance elements using metal oxide are of two types: bipolar and nonpolar. The voltage and current necessary to transit between a low-resistance state and a high-resistance state differ in polarity in the bipolar type and remain unchanged in either polarity in the nonpolar type. A nonpolar variable-resistance element can perform a memory operation in only one direction. Accordingly, it is possible to configure a cross-point cell array where cells, each composed of a series connection of a variable-resistance element and a diode, are arranged at the intersections of word lines and bit lines. The cell area of a cross-point cell using a diode can be decreased and it is easy to cause the cross-point cell to have a three-dimensional structure. Therefore, cross-point cells are suitable for stacking cell arrays to achieve a larger capacity.
A method of reading a cross-point cell array is as follows. Suppose voltage VREAD is applied to memory cells in a read operation.
When a memory operation is not carried out, the word lines and the bit lines are all at 0 V. All the word lines are raised to VREAD, activating a standby state in which a read operation can be performed. At this time, a reverse bias is applied to the diodes of all of the cells. There is reverse bias leakage in a diode. Therefore, imperceptible reverse current flows in each cell. When the number of cells included in the cell array is large, the sum of leakage currents occupies a large proportion of the consumption current of the entire memory.
When a specific cell is read, the selected word line is dropped from VREAD to 0 V and the selected bit line is set at VREAD. Since VREAD is applied to the cell at the interconnection of the selected word line and selected bit line, current corresponding to the resistance of the resistance element flows.
The both ends of each of the cells on the selected word line excluding the selected cell are at 0 V and the both ends of each of the cells on the bit line excluding the selected cell are at VREAD. Therefore, the potential difference between both ends of each of those half-selected cells (cells of which one of the word line and bit line connected to the cell is selected state and the other is unselected state) is 0 V, with the result that no current flows. In a read operation, too, a reverse bias of VREAD is applied to the unselected cells excluding the half-selected cells, which permits reverse leakage current to flow. The sum of the leakage currents contributes to consumption current.
Such a method of applying a voltage to the cell array can eliminate the effect of half-selected cells in reading the selected cell, enabling a wider read operation margin. However, this causes the problem of increasing leakage current. As a result, the size of the cell array cannot be made larger. Moreover, in a read operation, the number of cell arrays activated at the same time is limited and therefore the band width cannot be increased.
If a diode constituting a cross-point cell is defective and the word line and bit line are short-circuited, an unselected reverse bias state is produced and therefore current cannot be limited, resulting in a significant increase in the consumption current. If such a short circuit occurs, there is a possibility that the entire cell array cannot be read.
Another method of applying a word line voltage and a bit line voltage is as follows. When a memory operation is not performed, the word lines and bit lines are all set at 0 V. In the standby state, VREAD/2 is applied to all the word lines and all the bit lines. At this time, the voltage applied between the both ends of each of all the cells is 0 V and therefore no leakage current flows.
When a specific cell is read, the selected word line is set at 0 V and the selected bit line is set at VREAD. At this time, a selected word line voltage of 0 V and an unselected bit line voltage of VREAD/2 are applied to the half-selected cells on the selected word line and an unselected word line voltage of VREAD/2 and a selected bit line voltage of VREAD are applied to the half-selected cells on the selected bit line. That is, a forward bias of VREAD/2 is applied to the half-selected cells. If the nonlinearity of the current characteristic of the diode is strong and current with a forward bias of VREAD/2 is sufficiently smaller than that with a forward bias of VREAD, data in the selected cell can be read with a sufficient margin. Since both the word line voltage and bit line voltage are VREAD/2 in the unselected cells, no current flows.
In this method of controlling the word line voltage and bit line voltage, leakage current flowing in the unselected cells is small and therefore many cell arrays can be activated at the same time. Consequently, the band width can be increased.
However, in this method, the bias to the half-selected cells is not at 0 V. Therefore, if the number of half-selected cells becomes larger, the sum of their currents also becomes larger, decreasing the read margin. Accordingly, it is difficult to make the size of the cell array larger, decreasing the cell occupancy, which causes the problem of increasing the chip area.
Therefore, it has been hoped that a nonvolatile semiconductor memory device capable of preventing a decrease in the read margin of a variable-resistance element using a VREAD/2 bias method and a method of reading the same will be developed.
As for the related art, a memory device has been developed which monitors leakage current in the unselected cells (not cross-point cells) at the time of precharging, holds information temporarily in a capacitor, and cancels the leakage current on the basis of the held information in a read operation (refer to, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2006-228414).
In addition, a memory device has been developed which measures and compensates for leakage current in the unselected memory elements (cross-point cells) and then measures current in the selected memory element (refer to, e.g., Jpn. Pat. No. 4047315).